1. Field of the Invention
The present invention relates to the design of a semiconductor package; and, in particular, the present invention relates to a semiconductor package designed for high electrical and thermal dissipation performances.
2. Discussion of the Related Art
Semiconductor devices are becoming larger, integrating a larger number of circuits, and operating at increasingly higher clock frequencies. As a result, semiconductor devices are requiring, without compromising reliability, packages of increasingly higher lead count, and higher electrical and thermal performances.
In the prior art, conventional plastic molded packages can dissipate up to 2 watts of power. With some improvements in the lead frame, and by adding a heat spreader or heat sink, a plastic molded package can dissipate up to 4 watts. A further improvement in power dissipation can be achieved by attaching the semiconductor device, also called the semiconductor "die", onto an integral heat sink. Such a heat sink typically has a surface exposed to the ambient to conduct heat away from the package. An example of such a package, also called a "thermally enhanced" package, is shown in FIG. 1.
FIG. 1 shows a thermally enhanced package comprising a semiconductor die 105 attached by a layer of thermally conductive epoxy to a metallic heat sink 101. The input and output terminals of semiconductor die 105 are electrically coupled to connection terminals ("leads") of a lead frame 103 by wire bonds 104, which connect the bonding pads of semiconductor die 105 to individual leads in lead frame 103. Lead frame 103 attaches to heat sink 101 by a layer of dielectric adhesive 107. The thermally enhanced package is encapsulated in a plastic molding 102. In package 100, high thermal dissipation is achieved by attaching semiconductor die 105 directly onto the lower surface of heat sink 101 using a thermally conductive epoxy layer 106.
Although plastic molded packages are typically of high reliability, the incorporation of a heat sink in a thermally enhance plastic molded package, such as package 100 of FIG. 1, leads to failures which are directly related to the design and the material used in the heat sink. For example, heat sink 101 is often made of aluminum. The large difference between the thermal expansion coefficients (TCE) of the silicon die, at 3 ppm/.degree. C., and of aluminum, at 25 ppm/.degree. C. induces significant strain on semiconductor die 105. Such strain causes die-cracking and thus a package failure. For this reason, in the prior art, semiconductor die sizes are kept well below 10.times.10 mm to minimize the induced stress. Alternatively, a heat sink material with lower TCE can be chosen to minimize the large mismatch in the heat sink's and the semiconductor die's coefficients of thermal expansion.
A similar mismatch in TCEs exists between heat sink 101 and the plastic molding 102. Typically, a plastic molding compound has a TCE of about 17 ppm/.degree. C. The thermal cycle package 100 experiences during assembly and normal operations induces high stress at the metal-to-molding interface (i.e. between heat sink 101 and plastic molding 102) which can lead to delamination, cracking of the molding, and die failures. For this reason, a close matching of the TCEs of heat sink 101 to plastic molding 102 is very desirable.
During the assembly of package 100, plastic molding 102 shrinks significantly after the molding operation and during post-mold curing, which is typically carried out at or about 175.degree. C. The shrinking molding causes significant stress at the metal-to-molding interface, which can lead to delamination. Delamination is very undesirable and usually causes long-term reliability failures. Delamination can be minimized by including on the heat sink "locking" features, which strengthen mold adhesion, and by choosing a heat sink material with a TCE closer to that of the molding compound.
In the prior art, frequency performance is limited by the electrical parasitic impedances of the lead frame to 50 MHz or less. The lead frame usually consists of a single metal layer without the ability to provide controlled impedance connections. U.S. Pat. No. 4,891,687, entitled "Multilayer Molded Plastic IC Package", to Mallik et al, filed on Jan. 27, and issued on Jan. 2, 1990, discloses a package achieving a high electrical performance. However, the package disclosed in U.S. Pat. No. 4,891,687 requires two lead frames, and hence, such package is significantly more costly than a conventional plastic molded package.
Furthermore, the prior art's use of long wire bonds between the semiconductor die and the lead frame increases the impedances of ground connections. A high impedance to a ground connection results in "ground bounce" and other electrical noises which further restrict the overall electrical performance of the conventional plastic molded package. In logic semiconductor devices, which usually require high lead counts, about 25% of the leads in each package are used for power and ground connections. The large number of leads devoted to power and ground connections significantly reduces the number of pins available for signal connections, which usually determine the level of available performance.